A direct memory bit line access interface is important for testing and characterizing memory devices within integrated circuits. This interface allows execution of measurement operations by providing access to selected memory bit lines. The interface provides access for externally connected instrumentation to have a direct electrical connection to memory cells allowing measurement and characterization operations to be carried out. Critical measurements executable by direct electrical connection are bit line leakage measurements, bit line capacitance characterization, bit line to bit line short detection, memory cell current/voltage characterization, and memory cell operation with external voltage levels.
With reference to FIG. 1, a direct memory bit line access interface 100 provides connection to a particular set of bit lines within a large array of memory bit lines 110 within an internal memory of an integrated circuit. A memory access interface register 1201 . . . 120n selects a particular set of bit lines, senses the bit line data values, and retains a plurality of values read. The direct memory bit line access interface 100 also manages connection of a retained bit line value to one of several data pads 130 of the integrated circuit. The direct memory bit line access interface 100 also provides programming capabilities for the memory cells connected to by the memory bit lines 110.
With reference to FIG. 2, a particular set of memory bit lines 210 associated with a memory access register element 120, connect to the respective inputs of a register of sense amps 2201 . . . 220n (i.e., sense amplifiers). Outputs of the sense amps 2201 . . . 220n connect to a register of bidirectional storage element 2301 . . . 230n. The bidirectional storage element 2301 . . . 230n connect to a bidirectional data multiplexer 240. The bidirectional data multiplexer 240 has an output bidirectional data line 250 connected to a data pad (not shown). The memory bit lines 210 also connect to the inputs of a memory bit line multiplexer 260. The memory bit line multiplexer 260 has an output memory access line 290 connected to a data pad (not shown).
With reference to FIG. 3, a memory bit line 310 of a page register element 300 connects to an input of a sense amp 220. An output of the sense amp 220 connects to a bidirectional storage element 230. The bidirectional storage element 230 also connects to a bidirectional data line 350 and a programming driver 360. An output of the programming driver 360 connects to the memory bit line 310. The memory bit line 310 is connected to a memory access line 390 through a memory access gate 370. The memory access gate is enabled by a connection to a select signal at the output of an address select gate 380. The address select gate 380 is activated with an application of address bits at address bit lines 385 that correspond to an address of the page register element 300 or address of a memory bit line.
The memory access interface register 1201 . . . 120n (FIG. 1) includes several memory access register elements 120 (FIG. 2), each of which comprises a page register element 300 (FIG. 3) for each memory bit line 310 to which it is connected. The bidirectional data line 350 and the memory access line 390 connect to the bidirectional data multiplexer 240 and the memory bit line multiplexer 260 respectively.
Typically, a memory access gate is activated by connection to an address decoder gate within a memory bit line selection scheme. The address decoder is repeated for each page register element. An address decoder gate may become large and complex depending upon the number of address selection bits required in the selection scheme. The size of each address decoder gate and an instantiation of one decoder gate per bit line selected requires die area. Unless an address decoder scheme becomes additionally complex, only one address and, therefore, only one bit line, is selectable at a time. It is desirable to be able to have access to bit lines and avoid having additional logic incorporating a substantial amount of silicon area at each bit line instance. It is further desirable to be able to select multiple page register elements simultaneously and independently.